The present disclosure relates generally to memory devices and, more particularly, to memory devices implementing synchronous semiconductor memory techniques.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present techniques, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Generally, a computing system may include an electronic device that, in operation, communicates information via electrical signals. For example, a computing system may include a processor communicatively coupled to a memory device, such as a dynamic random-access memory (DRAM) device implemented on a dual in-line memory module (DIMM). In this manner, the processor may communicate with the memory device, for example, to retrieve executable instructions, retrieve data to be processed by the processor, and/or store data output from the processor, by means of command and/or address signals (CA signals). These CA signals may be supplied to a common bonding pad, for example, a pin, an external terminal, or the like.
In synchronous semiconductor memory, CA signals are provided to the memory device in synchronism with an external clock signal. In other words, the external clock signal and the CA signals are validated together with a change of a signal, such as a chip select signal, from, for example, a disabled state to an enabled state (e.g., logical low to logical high, or vice versa, based on logical components implemented in the memory device). In the memory device, these CA signals are latched by latching circuitry in response to an enabled latch control signal. A system controller may produce this latch control signal during a set-up time during the change of the chip select signal from the disabled state to the enabled state. Thus, delay circuitry may be provided to delay the arrival of the CA signals to the latch to match an arrival time of the enabled latch control signal from the system controller. However, this delay circuitry may consume an undesired amount of power while the memory device is unselected (e.g., disabled chip select signal), for example, due to power consumed in response to logical state changes of the CA signal transmitted through delay circuitry while the chip select signal is disabled.